Manuscript Number : IJSRSET207347

Design and Construction of 3 x 3 Bits Programmable Logic Array (PLA) Circuit

Authors(4) :-Sanda Win, San San Htwe, Sandar Win, Myint Myint Swe

A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND gate s for N input variables and for M outputs from PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms. The Programmable Logic Array (PLA) has a programmable AND array followed by a programmable OR array. Programmable Logic Array (PLA) circuit is built by using AND gates and OR gates. The 3x 4 bits data can be stored in this circuit. The large storage data bits of PLA circuit store by a using large AND-OR array with lots of inputs and product terms, and programmable connections. Programmable Logic Array circuit functions as ROM circuit.

Authors and Affiliations

Sanda Win
Natural Science Department, UCSTaungoo, Taungoo, Bago, Myanmar
San San Htwe
Natural Science Department, UCSTaungoo, Taungoo, Bago, Myanmar
Sandar Win
Natural Science Department, UCSTaungoo, Taungoo, Bago, Myanmar
Myint Myint Swe
Natural Science Department, UCSTaungoo, Taungoo, Bago, Myanmar

Programmable, Array, Data, Logic, Bit

  1. Andres, kent (October 1970) “A Texas instruments Application Report: MOS programmable logic arrays Texas instruments”, Bulletin CA-158.
  2. Hayes, Monson, Schaum’s “Outline of Digital Signal Processing”. New York: McGraw-Hill, 1998.
  3. Dahnoun, Naim “Digital Signal Processing Implementation Using the TMS320C6000DSP Platform” Reading, Mass: Addison-Wesley Longman, 2000.
  4. Kuo, Sen, and  Bob Lee “Real-Time Digital Signal Processing Implementations Applications and Experiments with the TMS320C55x”, New York: John Wiley & Sons, 2001

Publication Details

Published in : Volume 7 | Issue 3 | May-June 2020
Date of Publication : 2020-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 179-183
Manuscript Number : IJSRSET207347
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Sanda Win, San San Htwe, Sandar Win, Myint Myint Swe, " Design and Construction of 3 x 3 Bits Programmable Logic Array (PLA) Circuit, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 7, Issue 3, pp.179-183, May-June-2020. Available at doi : https://doi.org/10.32628/IJSRSET207347      Journal URL : https://res.ijsrset.com/IJSRSET207347

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