Manuscript Number : IJSRSET18413145

Power Optimization for ASIC Design (Low power ASIC)

Authors(1) :-Dr. Hitesh H Vandra

The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce feature size. Scaling of feature sizes in semiconductor technology has been responsible for increasingly higher computational capacity of silicon. However, questions regarding the limits of scaling have arisen in recent years due to the presence of leakage. As the supply voltage is lowered to satisfy the performance requirement, the threshold voltage has to be scaled, which increases leakage. More than 40% of the total power consumption is due to leakage of the transistor is in DSM. This leakage will increase with scaling become comparable with switching power. The goal of this paper is to analyse different low power circuits and optimization techniques to improve the power dissipation with the use of power gating components, retention registers, level shifters, isolation cells etc.

Authors and Affiliations

Dr. Hitesh H Vandra
Shri J M Sabva Institute of Engineering and Technology, Botad, Gujarat, India

ASIC, Design Optimization, High- Performance, Low-Power

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Publication Details

Published in : Volume 1 | Issue 1 | 2014
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 258-265
Manuscript Number : IJSRSET18413145
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Dr. Hitesh H Vandra, " Power Optimization for ASIC Design (Low power ASIC) , International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 1, pp.258-265, -2014. Journal URL : https://res.ijsrset.com/IJSRSET18413145

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