Manuscript Number : IJSRSET1841304

Review of Energy Saving Strategies for DRAM

Authors(1) :-Sai Kiran Talamudupula

The ever increasing power consumption of the components within a computing system have resulted in tremendous costs and substantial failure rates which are a roadblock in achieving optimal performance at reasonable costs. To mitigate these issues, strategies that reduce the dynamic power consumption of these components are needed. In this paper, we review a survey a subset of those strategies with their salient features and their efficacy in providing energy savings. The paper reviews energy saving strategies proposed and verified in both simulators and real-time systems.

Authors and Affiliations

Sai Kiran Talamudupula
BIOS Engineer, Intel Corporation, Chandler, Arizona

DRAM Power Management, Power States.

  1. A. Intel Power Governor. https://software.intel.com/en- us/articles/intel-power-governor.
  2. Intel Software Developer's Manual. https://software.intel.com/en-us/articles/intel-sdm
  3. N. Almoosa, W. Song, Y. Wardi and S. Yalamanchili. A Power Capping Controller for Multicore Processors. In 2012 American Control Conference (ACC), pages 4709-4714. June 2012.
  4. D.H. Bailey et. Al. The NAS Parallel Benchmarks Summary and Preliminary Results. In Proceedings of the 1991 ACM/IEEE conference on Supercomputing, pages 158-165, 1991.
  5. T. Vogelsang. Understanding the Energy Consumption of Dynamic Random Access Memories. In MICRO 2010.
  6. H. David, E. Gorbatov, U.R. Hanebutte, R. Khannal, and C. Le RAPL: Memory Power Estimation and Capping. In Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, ISLPED'10, pages 189-194, New York, NY, USA, 2010. ACM.
  7. V. Anagnostopoulou et. al. Barely alive memory servers: Keeping data active in a low-power state. in ACM Journal on Emerging Technologies in Computing Systems, Special issue on Sustainable and Green Computing Systems, April 2012.
  8. R. Ge, X. Feng, W. Feng, and K.W. Cameron. CPU MISER: A Performance Directed, Run-time System for Power-aware Clusters. In Parallel Processing, 2007. ICPP 2007. International Conference on, page 18, Sep. 2007.
  9. R. Ge, X. Feng, Y. He, and P. Zou. The Case for Cross- component Power Coordination on Power Bounded Systems. In 2016 45th International Conference on Parallel Processing (ICPP), pages 516-525, Aug 2016.
  10. R. Ge, X. Feng, S. Song, H.C. Chang, D. Li, and K.W. Cameron. PowerPack: Energy Profiling and Analysis of High- performance systems and Applications. Parallel and Distributed Systems, IEEE Transactions on, 21:658-671, 2010.
  11. A. Amin et. al. Rank-aware cache replacement and write buffering to improve DRAM energy efficiency. In Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, pp. 383-388, ACM, 2010.
  12. S. Huang and W. Feng. Energy-efficient Cluster Computing via Accurate Workload Characterization. In Cluster Computing and the Grid, 2009. CCGRID'09. 9th IEEE/ACM International Symposium on, pages 68- 75, May 2009.
  13. R. Ayoub et. al. Energy efficient proactive thermal management in memory subsystem. In International Symposium on Low-Power Electronics and Design (ISLPED), pp. 195-200, IEEE, 2010.
  14. C. Isci and M. Martonosi. Runtime Power Monitoring in High- end Processors: Methodology and empirical data. In Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, MICRO 36, pages 93-, Washington, DC, USA, 2003. IEEE Computer Society.
  15. K. Kandalla, E.P. Mancini, S. Sur, and D.K. Panda. Designing Power-aware Collective Communication Algorithms for InfiniBand Clusters. In Parallel Processing (ICPP), 2010 39th International Conference on, pages 218-227, 2010.
  16. Kristopher Keipert, Gaurav Mitra, Vaibhav Sundriyal, Sarom S. Leang, Masha Sosonkina, Alistair P. Rendell, and Mark S. Gordon. Energy Efficient Computational Chemistry: Comparison of x86 and ARM Systems. Journal of Chemical Theory and Computation, 11(11):5055-5061, 2015. PMID:26574303.
  17. M. Bi et. al. Delay-Hiding Energy Management Schemes for DRAM. In IEEE HPCA 2010.
  18. Gary Lawson, Vaibhav Sundriyal, Masha Sosonkina, and Yuzhong Shen. Runtime Power Limiting of Parallel applications on Intel Xeon Phi Processors. In Proceedings of the 4th International Workshop on Energy Efficient Supercomputing, E2SC '16, pages 39- 45, Piscataway, NJ, USA, 2016. IEEE Press.
  19. M.Y. Lim, V.W. Freeh, and D.K. Lowenthal. Adaptive, Transparent Frequency and Voltage scaling of Communication Phases in MPI Programs. In Proceedings of the 2006 ACM/IEEE conference on Supercomputing, 2006.
  20. K. Chandrasekhar, B. Akesson and K. Goossens. Run- time power-down strategies for real-time SDRAM memory controllers. In Proceedings of the 49th Annual DAC, pp. 988-993, ACM, 2012.
  21. K. Ma, X. Li, W. Chen, C. Zhang, and X. Wang. GreenGPU: A Holistic Approach to Energy Efficiency in GPU-CPU Heterogeneous Architectures. In 2012 41st International Conference on Parallel Processing, pages 48-57, Sept 2012.
  22. Jayanth Srinivasan. An Overview of Static Power Dissipation. Technical report.
  23. V. Sundriyal and M. Sosonkina. Per-call Energy Saving Strategies in All-to-all Communications In Proceedings of the 18th European MPI Users' Group conference on Recent advances in the message passing interface, EuroMPI'11, pages 188-197, Berlin, Heidelberg, 2011. SpringerVerlag.
  24. G. Chen, R. Shetty, M. Kandemir, N. Vijaykrishnan, M. Irwin and M. Wolczko. Tuning garbage collection for reducing memory system energy in an embedded java environment.In ACM Transactions on Embedded Computing Systems. 2002.
  25. V. Sundriyal and M. Sosonkina. Initial Investigation of a Scheme to use Instantaneous CPU Power Consumption for Energy Savings format. In Proceedings of the 1st International Workshop on Energy Efficient Supercomputing, E2SC '13, pages 1:1-1:6, New York, NY, USA, 2013. ACM.
  26. M. Chen et. al. Coordinating Processor and Main Memory for Efficient Server Power Control. In ICS 2011.
  27. V. Sundriyal and M. Sosonkina. Joint Frequency Scaling of Processor and DRAM. The Journal of Supercomputing, 72(4):1549-1569, 2016.
  28. V DeLaLuz et. al. Automatic data migration for reducing energy consumption in multi-bank memory systems," in DAC, 2002, pp. 213- 218, IEEE, 2002
  29. V DeLaLuz, M. Kandemir, N. Vijaykrishnan, M. Irwin, A. Sivasumbramaniam, and I. Kolcu. Compiler-directed array interleaving for reducing energy in multi-bank memories. In ASPDAC 2002.
  30. V DeLaLuz, M. Kandemir, N. Vijaykrishnan, M. Irwin and A. Sivasumbramaniam. DRAM energy management using software and hardware directed power mode control. In HPCA 2001.
  31. V DeLaLuz, M. Kandemir, N. Vijaykrishnan, M. Irwin and A. Sivasumbramaniam. Scheduler Based DRAM Energy Management. DAC 2002.
  32. V. Sundriyal, M. Sosonkina, and A. Gaenko. Runtime Procedure for Energy Savings in Applications with Point-to- point Communications. In Computer Architecture and High- Performance Computing (SBAC-PAD), 2012 IEEE 24th International Symposium on, pages 155-162, 2012.
  33. Q. Deng et. al. MultiScale: Memory System DVFS with Multiple Memory Controllers. ISPLED 2012.
  34. DRAM Basics. Chapter 12. https://www.ece.cmu.edu/~ece740/f11/lib/exe/fetch.php?media =wiki:lectures:onur-740-fall11-lecture25-mainmemory.pdf
  35. Q. Deng et. al. Memscale: active low-power modes for main memory. ACM SIGPLAN Notices, vol. 46, no. 3, pp. 225-238, 2011.
  36. V. Sundriyal, M. Sosonkina, and Z. Zhang. Achieving Energy Efficiency During Collective Communications. Concurrency and Computation: Practice and Experience, 25(15):2140-2156, 2013.
  37. B. Diniz, D. Guedes, W. Meira Jr, and R. Bianchini, “Limiting the power consumption of main memory," in ACM SIGARCH Computer Architecture News, vol. 35, pp. 290-301, ACM, 2007.
  38. X. Fan, C. Ellis, and A. Lebeck, “Memory controller policies for DRAM power management," in Proceedings of the 2001 international symposium on Low power electronics and design, pp. 129-134, ACM, 2001.
  39. M. Floyd, S. Ghiasi, T. Keller, K. Rajamani, F. Rawson, J. Rubio, and M. Ware, “System power management support in the IBM POWER6 microprocessor," IBM Journal of Research and Development, vol. 51, no. 6, pp. 733-746, 2007.
  40. H. Huang, P. Pillai, and K. Shin, “Design and implementation of power-aware virtual memory," USENIX Annual Technical Conference, pp. 57-70, 2003.
  41. H. Huang, K. Shin, C. Lefurgy, and T. Keller, “Improving energy efficiency by making DRAM less randomly accessed," in Proceedings of the 2005 international symposium on Low power electronics and design, pp. 393-398, ACM, 2005.
  42. I. Hur and C. Lin, “A comprehensive approach to DRAM power management," in 14th International Symposium on High Performance Computer Architecture, 2008. HPCA., pp. 305-316, IEEE, 2008.
  43. S. Irani, S. Shukla, and R. Gupta, “Online strategies for dynamic power management in systems with multiple power-saving states," ACM Transactions on Embedded Computing Systems (TECS), vol. 2, no. 3, pp. 325-346, 2003.
  44. M. Kandemir, U. Sezer, and V. Delaluz, “Improving memory energy using access pattern classification," in International Conference on Computer-Aided Design, pp. 201-206, IEEE Press, 2001.
  45. B. Khargharia, S. Hariri, and M. S. Yousif, “Self- optimization of performance-per-watt for interleaved memory systems," in 14th international conference on High performance computing, HiPC'07, (Berlin, Heidelberg), pp. 368-380, Springer-Verlag, 2007.
  46. H. Koc, O. Ozturk, M. Kandemir, and E. Ercanli, “Minimizing energy consumption of banked memories using data recomputation," in International Symposium on Low Power Electronics and Design, 2006., pp. 358- 361, 2006.
  47. A. Lebeck, X. Fan, H. Zeng, and C. Ellis, “Power aware page allocation," ACM SIGPLAN Notices, vol. 35, no. 11, pp. 105-116, 2000.
  48. X. Li, R. Gupta, S. Adve, and Y. Zhou, “Cross- component energy management: Joint adaptation of processor and memory," ACM Transactions on Architecture and Code Optimization (TACO), vol. 4, no. 3, p. 14, 2007.
  49. X. Li, Z. Li, F. David, P. Zhou, Y. Zhou, S. Adve, and S. Kumar, “Performance directed energy management for main memory and disks," in ACM SIGARCH Computer Architecture News, vol. 32, pp. 271-283, ACM, 2004.
  50. S. Liu, K. Pattabiraman, T. Moscibroda, and B.Zorn, “Flikker: Saving DRAM refresh-power through critical data partitioning," ACM SIGPLAN Notices, vol. 46, no. 3, pp. 213-224, 2011.
  51. C. Lyuh and T. Kim, “Memory access scheduling and binding considering energy minimization in multi-bank memory systems," in Proceedings of the 41st annual DAC, pp. 81-86, ACM, 2004.
  52. K. T. Malladi, F. A. Nothaft, K. Periyathambi, B. C. Lee, C. Kozyrakis, and M. Horowitz, “Towards energy- proportional datacenter memory with mobile DRAM," in ISCA, pp. 37 -48, june 2012.
  53. D. Meisner, B. Gold, and T. Wenisch, “PowerNap: eliminating server idle power," ACM Sigplan Notices, vol. 44, no. 3, pp. 205-216, 2009.
  54. J. Mukundan and J. F. Martinez, “MORSE: Multi- objective reconfigurable self-optimizing memory scheduler," HPCA, vol. 0, pp. 1-12, 2012.
  55. O. Ozturk, G. Chen, M. Kandemir, and M. Karakoy, “Cache miss clustering for banked memory systems," in IEEE/ACM international conference on Computer- aided design, ICCAD '06, pp. 244-250, ACM, 2006.
  56. O. Ozturk and M. Kandemir, “ILP-Based energy minimization techniques for banked memories," ACM Trans. Des. Autom. Electron. Syst., vol. 13, pp. 50:1-50:40, July 2008.
  57. V. Pandey, W. Jiang, Y. Zhou, and R. Bianchini, “DMA- aware memory energy management," in HPCA, pp. 133- 144, feb. 2006.
  58. V. Sundriyal, M. Sosonkina, and Z. Zhang. Automatic Runtime Frequency Scaling System for Energy Savings in Parallel Applications. The Journal of Supercomputing, 68(2):777-797,2014.
  59. Vaibhav Sundriyal, Ellie Fought, Masha Sosonkina, and Theresa L. Windus. Power Profiling and Evaluating the Effect of Frequency Scaling on NWChem. In Proceedings of the 24th High Performance Computing Symposium, HPC '16, pages 19:1-19:8, San Diego, CA, USA, 2016. Society for Computer Simulation International.
  60. Vaibhav Sundriyal, Ellie Fought, Masha Sosonkina, and Theresa L. Windus. Evaluating effects of application based and automatic energy saving strategies on NWChem. In Proceedings of the 25th High Performance Computing Symposium, HPC '17, pages 16:1-16:12, San Diego, CA, USA, 2017. Society for Computer Simulation International.
  61. Vaibhav Sundriyal and Masha Sosonkina. Runtime power- aware energy-saving scheme for parallel applications. 2015.
  62. Vaibhav Sundriyal, Masha Sosonkina, Alexander Gaenko, and Zhao Zhang. Energy saving strategies for parallel applications with point-to-point communication phases. Journal of Parallel and Distributed Computing, 73(8):1157 - 1169, 2013.
  63. A. Vishnu, S. Song, A. Marquez, K. Barker, D. Kerbyson, K. Cameron, and P. Balaji. Designing Energy Efficient Communication Runtime Systems for Data Centric Programming Models. In Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing, GREENCOM- CPSCOM '10, pages 229-236, Washington, DC, USA, 2010. IEEE Computer Society.
  64. P. Zhou et. al. Dynamic Tracking of Page Miss Ratio Curve for Memory Management. ACM SIGOPS 2004.
  65. Honzong Zheng et. al. Mini-Rank: Adapting DRAM Architecture for Improving Memory Power Efficiency. MICRO 2008.
  66. D.H Yoon, J. Chang, N. Muralimanohar and P. Ranganathan. BOOM: Enabling Mobile Memory Based Low-Power Server DIMMs. ISCA 2012.
  67. Kevin K. Chang et. al. Understanding Reduced Voltage Operations in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms. Proceedings of the ACM on Measurement and Analysis of Computing Systems. Volume 1, Issue 1, June 2017.
  68. S. Phadke and S. Narayanasamy. MLP Aware Heterogeneous Memory Systems. IEEE DATE 2011.
  69. C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T.W. Keller. Energy management for commercial servers. Computer, 36(12):39- 48, December 2003.
  70. S. Borkar. The exascale challenge, 2011. Keynote speech, the 12th International Conference on Parallel Architectures and Compilation Techniques.
  71. R. Gonzalez, B. M. Gordon, and M. A. Horowitz. Supply and Threshold Voltage Scaling for Low Power CMOS. IEEE Journal of Solid-State Circuits, 32(8):1210-1216, Aug 1997.
  72. G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, and M. L. Scott. Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In Proceedings Eighth International Symposium on High Performance Computer Architecture, pages 29-40, Feb 2002.
  73. Linux Kernel Governors. https://www.kernel.org/doc/Documentation/cpufreq/governors.t xt. Online].
  74. V Pallipadi and A Starikovskiy. The Ondemand Governor: Past, Present and Future. 2:223-238, 01 2006
  75. R. Efraim, R. Ginosar, C. Weiser, and A. Mendelson. Energy Aware Race to Halt: A Down to Earth Approach for Platform Energy Management. IEEE Computer Architecture Letters, 13(1):25-28, Jan 2014.
  76. J. P. Halimi, B. Pradelle, A. Guermouche, N. Triquenaux, A. Laurent, J. C. Beyler, and W. Jalby. Reactive DVFS Control for Multicore Processors. In 2013 IEEE International Conference on Green Computing and Communications and IEEE Internet of Things and IEEE Cyber, Physical and Social Computing, pages 102-109, Aug 2013.
  77. Vaibhav Sundriyal, Masha Sosonkina, Fang Liu, and Michael W. Schmidt. Dynamic Frequency Scaling and Energy Saving in Quantum Chemistry Applications. In IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum, pages 837-845, 2011.
  78. A. Marathe et. al. A Run-time System for Power Constrained HPC Applications. International Conference on High Performance Computing. ISC 2015.
  79. Z. Wang and X. Hu, “Energy-aware variable partitioning and instruction scheduling for multibank memory architectures," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 10, no. 2, pp. 369-388, 2005.
  80. H. Zheng and Z. Zhu, “Power and Performance Trade- Offs in Contemporary DRAM System Designs for Multicore Processors," IEEE Transactions on Computers, vol. 59, no. 8, pp. 1033-1046, 2010.
  81. D. Kaseridis, J. Stuecheli, and L. K. John, “Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era," in MICRO, MICRO-44 '11, (New York, NY, USA), pp. 24-35, ACM, 2011.
  82. H. Kim and I.-C. Park, “High-performance and low- power memory-interface architecture for video processing applications," IEEE Transactions on Circuits and Systems for Video Technology,, vol. 11, pp. 1160 - 1170, nov 2001.
  83. Y. Li and T. Zhang, “Reducing DRAM Image Data Access Energy Consumption in Video Processing," IEEE Transactions on Multimedia, vol. 14, pp. 303-313, april

The best gift for any occasion is the Rubik's Cube. The famous 3D puzzle can easily be solved with the online cube solver.

Publication Details

Published in : Volume 4 | Issue 1 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1332-1340
Manuscript Number : IJSRSET1841304
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Sai Kiran Talamudupula, " Review of Energy Saving Strategies for DRAM, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 1, pp.1332-1340, January-February-2018. Journal URL : https://res.ijsrset.com/IJSRSET1841304

Article Preview